The 3rd COE Postdoctoral and Doctoral Researchers
Technical Presentation

Program (20 mins each: 15 mins presentation and 5 mins discussion)

1. "Novel View Telepresence Using Omni-directional Live Videos"
   石川 智也 ( 視覚情報メディア講座 : D2 )
   Tomoya Ishikawa ( Vision and Media Computing Lab. : D2 )
   

   [Abstract]
   In the ubiquitous environment, we can easily take the images which are captured at remote sites. With the environment, telepresence which enable us to see a virtualized remote site has been investigated. In this presentation, we propose a prototype system of novel view telepresence which can provide a feeling of being in a remote site to a user. The proposed system consists of a server for transmission of remote live videos and a client for generation of novel views. Thanks to the server-client system, a cost for view generation becomes low by distributing the processes into view-dependent and non-view-dependent processes. Furthermore, the system enables to transfer remote video streams. The user can see views interactively and immersively by using an HMD with a position and posture sensor.
   
   
   Top

2. "Improvement of Semi-automatic Location-based Photo Captioning Using Geographical Database"
   岩崎 季世子 ( 視覚情報メディア講座 : D2 )
   Kiyoko Iwasaki ( Vision and Media Computing Lab. : D2 )
   

   [Abstract]
   We have proposed a framework for semi-automatic location-based photo captioning by reference to a geographical database and relevant word extraction using web retrieval based on shooting position and orientation information. In this presentation, I describe two points to improve captioning efficiency: (1) changing positions corresponding to places, facilities and buildings in the geographical database from a point like a pair of latitude and longitude to a region occupied with an object, (2) referencing a Japanese lexicon in relevant word extraction process. I also show experimental results using a prototype system.
   
   
   Top

3. "Infrastructure Construction Tool for Localization System Using Visual Markers"
   中里 祐介 ( 視覚情報メディア講座 : D2 )
   Yusuke Nakazato ( Vision and Media Computing Lab. : D2 )
   

   [Abstract]
   To realize an augmented reality (AR) system using a wearable computer, the exact position and orientation of a user are required. User's position and orientation are sometimes estimated by recognizing visual markers pasted up on the ceilings or walls. Such a method needs 3D position information of markers in advance. However, much cost is necessary to measure alignment information of markers in a wide environment. In this presentation, we propose an infrastructure construction tool for visual marker-based wearable augmented reality. In the tool, 3D positions of markers are estimated from markers' images captured by a high resolution camera. Next, the tool assists administrator in repairing the pattern of illegal marker using AR technique.
   
   
   Top

4. "Design for Testability of Software-Based Self-Test for Processors"
   中里 昌人 ( コンピュータ設計学講座 : D2 )
   Masato Nakazato ( Computer Design and Test Lab. : D2 )
   

   [Abstract]
   In recent years, processors with high performance and rich functionality absolutely require accurate and at-speed testing. Though full scan approach is commonly used to its simplicity, it induces performance penalty, area overhead and excessive power consumption. To resolve these disadvantages, software-based self-test (SBST) methods receives much attention. In SBST, we test a processor by executing a sequence of instructions called a test program. Therefore, it enables at-speed testing with the normal operation of the processor.
   Some methods among the SBST methods generate a test program based on test program templates. These approach consists of a test generation for a module and the test program synthesized from test patterns. However, SBST using templates has a problem of error masking where some faults detected in a test generation for a module are not detected by the test program synthesized from the test.
   In this presentation, we propose a design for testability method for test programs of software-based self-test using test program templates. The proposed method achieves 100% template level fault efficiency in a sense that the proposed method completely resolves the problem of error masking. Moreover, the proposed method adds only observation points to the original design and it enables at-speed testing and does not induce delay overhead.
   
   
   Top

5. "A Non-scan DFT Method for RTL Circuits"
   岩田 浩幸 ( コンピュータ設計学講座 : D2 )
   Hiroyuki Iwata ( Computer Design and Test Lab. : D2 )
   

   [Abstract]
   
   With the progress of semiconductor technology, testing of VLSI becomes more difficult. Then, the design for testability(DFT) at higher level have been proposed to reduce the number of hardware elements. In this presentation, I will define the testable characteristics for RTL circuits. Then, I will show the DFT method based on the characteristics and the experimental results.
   
   Top

6. "A method to Reduce Over-testing for Path Delay Faults Using RTL Information"
   吉川 祐樹 ( コンピュータ設計学講座 : D2 )
   Yuuki Yoshikawa ( Computer Design and Test Lab. : D2 )
   

   [Abstract]
   
   With the progress of VLSI design and manufacturing technologies, the speed of VLSI circuits has increased in recent years. For high speed circuits, delay testing is an important technique to verify that a given logic operates correctly at the desired clock period. For a sequential circuit, a path is defined as an ordered set of gates between two flip-flops. Testing a path delay fault (PDF) on a path can detect a defect that induces a propagation delay beyond the specified clock period.
   In general, there are many false paths in a circuit. A transition at the starting point of a false path is never propagated to the ending point of the path during normal operation. Hence, a PDF on the false path does not affect the circuit performance even if it exists on the path, that is, the PDF should not be detected. However, for the circuit augmented by some design-for-testability technique, which is generally used to enhance testability, most of the false paths are tested. This becomes over-testing. The over-testing causes yield loss and some other problems. We proposed a method to reduce the over-testing.
   

NAIST Graduate School of Information Science