The 5th COE Postdoctoral and Doctoral Researchers
Technical Presentation

Date: Tuesday, August 24, 2004
Time 13:30 - 15:30
Place L1 Lecture room
Language: English (oral presentation), English/Japanese (question)
Chairperson: Atsushi Fujita ( Computational Linguistics Lab. : D3 ),
Osamu Tobe ( Information Technology Center : D2 )

Program (20 mins each: 15 mins presentation and 5 min discussion)

  1. "Test Application Time Reduction with a Dynamic Reconfigurable Scan Tree Architecture"
    Yannick Bonhomme ( Computer Design and Test Lab. : PD )

    [Abstract]
    VLSI circuit cost depends on the production cost and on the test cost. The test application time is an important part of the test cost, due to the price of the ATE (Automatic Test Equipment). Scan design techniques is often used in Integrated Circuits (ICs) or in System on Chips (SOCs) to facilitate the test generation and to increase the test quality. Unfortunately, scan design requires a large number of clock cycles to apply the test sequence to the circuit. In this context, we propose a scan tree architecture to reduce the test application time. This technique is based on a dynamic reconfiguration mode: the scan tree mode and the single scan. By this way, we can generate a scan tree architecture for any circuit. The proposed technique has no penalty on the number of test pins. Different optimizations: fan-out and area overhead are also possible. Experimental results show up to 88% of test application time saving and test data volume reduction in comparison with a single scan chain architecture.
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  2. "A Design for 2-pattern Testability of System-on-Chip Interconnects"
    嵯峨 佑介 ( コンピュータ設計学講座 : D2 )
    Yusuke Saga ( Computer Design and Test Lab. : D2 )

    [Abstract]
    System-on-chips (SoCs) are often used in ubiquitous computing systems. Testing crosstalk-induced faults on interconnects of SoC has become more important because of high integration of semiconductors. The faults can be tested by 2-pattern testing. 2-pattern testing means application of consecutive two test patterns and observation of one test response. In this presentation, we present two DFT methods for 2-pattern testability of interconnect. One DFT method utilizes EXTEST mode of IEEE P1500 wrappers and achieves 2-pattern test through a serial TAM. The other method doesn't use IEEE P1500 wrappers, but utilizes existing interconnects as much as possible in order to achieve 2-pattern test. In case studies, we show advantages that one of the proposed DFT methods is effective when designers adopt the IEEE P1500 wrappers, and hardware overhead of the another proposed DFT method is lower than that of our previous DFT method based on consecutive testability.
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  3. "Study on Adaptive Aiding for Plant Operation"
    劉 希未 ( システム制御・管理講座: D1 )
    Xiwei Liu ( System and Control Lab. : D1 )

    [Abstract]
    In this study, we analyzed human performance by using computational models and simulation, and evaluated the effects of various operation supports for a human supervisory control system. Through these analyses and evaluations, some adaptive aiding methods were proposed. Based on model human processor (Card etc., 1983), we presented a new framework of cognitive information-processing model incorporating with mental sate and attention. A mental model for fault diagnosis was built and validated by some simulation experiments. The human model could detect several failure causes according to the mental model and take countermeasures for them. Short-term and long-term memory models were constructed, by which we could parse human memory performance and evaluate some support methods for memory errors.
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  4. "Peripheral Bus Extension for Device Sharing over IP Network"
    広渕 崇宏 ( 情報科学センター : D1 )
    Takahiro Hirofuchi ( Information Technology Center : D1 )

    [Abstract]
    Personal computing with mobile computers and their peripheral devices becomes more popular. To use such devices more efficiently and improve their usability, people want to share the surrounding peripheral devices between computers without any modification of their own computing environments. The recent device sharing technologies in the pervasive computing area are not sufficient enough for the peripheral devices of personal computers, because these technologies do not provide the network-transparency for applications and device drivers. In this presentation, we propose peripheral bus extension over IP network as an advanced device sharing approach, which is based on the modern sophisticated peripheral interfaces and their support in the operating systems. In this approach, users can share diverse devices over networks without any modification of the existing operating system and applications. Furthermore, this approach has the interoperability between different operating systems.
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  5. "A Design of an information retrieval method based on TPO metadata"
    新井 イスマイル ( 情報科学センター : D1 )
    Ismail Arai ( Information Technology Center : D1 )

    [Abstract]
    A user searches some information in WWW by inputting circumstantial information such as time, position, occasion and favorite information written as keyword. In order to search efficiently the information which a user desires, An information retrieval reflecting various user's circumstantial information is expected. In such information retreaval, There are two requirements which are classification of circumstantial information and the retrieval technique making the best use of circumstantial information. In consideration of the requirements, we attached metadata in user's queries and web contents. We propose an information retrieval method that compare metadata of a user and contents. Then, we design and implement M3 search engine based on the proposal. As a result of evaluation, we showed the hit rate of M3 search engine is higher than one of full-text search engine and arrival time of M3 search engine is shorter than one of full-text search engine.
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  6. "One Method for Resolving Japanese Zero Pronouns"
    飯田 龍 ( 自然言語処理学講座 : D1 )
    Ryu Iida ( Computational Linguistics Lab. : D1 )

    [Abstract]
    We propose to enhance a machine learning model for coreference resolution by incorporating linguistically motivated contextual clues, such as the centering theory. In comparison to Soon et al.(2001), our model shows improvements arising from two sources: (i) the feature of local contextual factors and (ii) an augmentation of the learning model to take into account comparison between candidates. This model is applied to resolve Japanese zero-anaphors and outperforms earlier machine learning approaches.
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NAIST Graduate School of Information Science 21st Century COE Program