| 概要(Abstract)： |
The flexibility displayed by processors delivers time-to-market and cost advantages while falling short of performance and power goals, when compared to Application Specific Integrated Circuits. Such shortfalls can be addressed through the incorporation of application specific properties into the processor microarchitecture, thus increasing performance and reducing power consumption.
The overall approach that guides such customizations consists of the identification of application properties during compile time and their dynamic exploitation during program execution by the processor. The basic characteristics of these properties is that their existence can be statically identifiable by the compiler, and that they can lead to significant improvements in performance when exploiting their behavior dynamically. Such properties may consist of the control structure of the algorithm, the run-time data values and the code manipulating some data structures; for example, an array access, its stride, or its control structure. Microarchitectural features that can be enhanced with such application-specific information include the branch predictor, the cache subsystem, and the processor communication infrastructure; techniques aimed at all three are outlined in this talk.
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