While the synchronous-logic approach, a clock-based synchronization
approach, is still the de facto approach in digital circuits, some design
issues in a synchronous circuit become more and more challenging
specifically when the semiconductor technology continues to down-scale for
higher performance and higher circuit integration. These design issues
include operation robustness (affected by delay variations), high power
dissipation, high electromagnetic interference, etc. Conversely, the
asynchronous-logic design approach, a clock-less handshake approach, is a
promising alternative in alleviating such design issues in digital circuits.
Unsurprisingly, as predicted by the International Technology Roadmap for
Semiconductors (ITRS), asynchronous-logic is estimated to account for 17%
total circuitry of an integrated circuit (IC) chip from now, and up to 49%
in year 2024.
This presentation will provide a brief overview on asynchronous-logic with
the emphasis on low power/energy dissipation. This presentation will
describe some successful asynchronous-logic digital circuit examples
developed in Nanyang Technology University, Singapore, and delineate the
basic premises how power/energy dissipation is reduced by means of
asynchronous-logic. The examples given in this presentation demonstrate
that by means of appropriate design techniques, designs based on the
asynchronous-logic approach can feature superior (lower) power/energy
attributes over designs based on the prevalent synchronous-logic approach.
Kwen-Siong Chong received the Ph.D degree in electrical and electronic
engineering from Nanyang Technological University (NTU), Singapore, in 2007.
He is presently a Senior Research Scientist with Temasek Laboratories @ NTU,
Singapore. His research interests include asynchronous-logic VLSI designs,
low-voltage low power methodologies, audio signal processing and FPGA
prototyping. He has published 19 journal and conference papers, a book
chapter, and has been awarded with 2 patents. He is also a
co-PI/collaborator of research grants amounting more than S$2M. He is a
member of IEEE, a technical committee for IEEE VLSI Systems and Applications
of the IEEE Circuits and Systems (CAS) Society, and a committee member of
IEEE CAS Society, Singapore Chapter.