ゼミナール講演

日時平成 17年 2月7日(月) 4限 (15:10-16:40)
場所L1 講義室
講演者Kewal K. Saluja 教授
所属 ウィスコンシン大学
講演題目 A Three Way Attack on Testing Problem via Ranadom Access Scan
概要
Traditional testing research for testing VLSI circuits has stuck to the use of serial scan test architecture whose origin lies in keeping the hardware overhead low. However there has been a paradigm shift in cost factor - the transistor cost has been dropping exponentially whereas the test cost is starting to increase. We believe that adding more hardware then believed to be affordable by the traditional methods is acceptable provided the test cost can be reduced considerably.

In this talk we will discuss an alternative design for testability method that simultaneously addresses three limitations of the traditional scan methods namely, test data volume, test application time, and test power. For the audience not familiar with the testing methods, we will also include a brief tutorial on the prevalent design for testability methods and test generation algorithms. We will then provide a traveling salesman formulation of the test application time problem in random access scan environment. Our results show that the random access scan can simultaneously reduce the test time, test data, and test power.  

備考 本ゼミナールは,NAIST-IS COE 国際セミナーとの共催です.
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