[Abstract]
VLSI testing is an essential technology to realize dependable ubiquitous
systems because VLSI circuits are basic components of ubiquitous devices.
In VLSI testing, full scan design is widely adopted as a design for testability
(DFT) approach to reduce the complexity of testing today's VLSI circuits.
However, this design approach imposes high area and performance penalties.
In order to alleviate these penalties, partial scan design has been proposed
as a viable DFT approach. For the stuck-at fault model, which is a conventional
fault model, partial scan technique is well studied by many researchers.
However, for the delay fault model, which is used for testing high-speed
VLSI circuits, it is still not highly considered. We are now investigating
a method of delay testing using partial scan technique. In this talk, we
survey some existing approaches to test delay faults in full scan circuits,
and discuss our research objective and research plan for delay testing
using partial scan technique.
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