As research on artificial intelligence is advancing, neural networks that model the operation of brain neural circuits are used for computations such as machine learning using big data and combinatorial optimization. Although the performance of machine learning has been improved by deep learning using a multilayer neural network in which many nodes are stacked, there are problems that large amount of resources are required in terms of calculation amount and power consumption. A new technology that solves the above problems is neuromorphic computing, which is implemented by hardware by imitating not only the mechanism of brain firing but also its structure. By implementing neural networks at hardware level, large-scale integration and low power consumption can be achieved, and the above problems can be solved. Further, by using amorphous In-Ga-Zn-O (α-IGZO) of an oxide semiconductor that enables fabrication at room temperature and large-scale integration for a synapse of a network, neural network of similar performance with less computational resources and power consumption can be constructed.
In this paper, in order to evaluate the operation of the neuromorphic hardware, it was simulated using an associative memory algorithm. Moreover, assuming that the deviation of initial resistance of the oxide semiconductor is 20%, in the simulation of 3x3 pixels, it was found that the correction ratio of the associate memory of more than 80% can be obtained when the input pattern has difference pixel of about 30% compared to the memorized pattern. In the simulation of 6x6 pixels, it was found that the correction ratio of the associate memory of more than 80% can be obtained when the input pattern has difference pixel of about 20%. In the simulation of 9x9 pixels, it was found that the correction ratio of the associate memory of more than 80% can be obtained when the input pattern has difference pixel of about 10%.
In addition, operation verification was performed using the created neuromorphic hardware chips. There are 3 types of deposition structures for the created chips. The first one was that only argon gas was injected during sputtering, and the deviation of the initial resistance of the chip was 27%. It was confirmed that the operation of associate memory of 1 letter was possible in the experiment using the chip. The second one was that argon gas and oxygen were injected during sputtering, and the deviation was improved to 23%. This is because the influence from the external environment could be suppressed. It was confirmed that the operation of associate memory of 1 letter was possible. The last one was that light is irradiated on the deposition area of the chip having the second deposition structure, and the deviation was improved to 21%. This is because the free carriers generated by the light terminated non-uniform defects in the deposition area. It was confirmed that the operation of associate memory of 1 letter and 2 letter was possible.
In conclusion, the operation of the chip was confirmed, which can be created at low temperature and can be said to be a prototype of neuromorphic hardware using highly integrated oxide semiconductor synapses.