Title:Random Variation Aware Hardware Trojan Detection Through Power Based Side-Channel Analysis*
Abstract: Hardware security has become a growing concern in the design and test of chips since its manufacturing processes are becoming increasingly vulnerable due to malicious activities and alterations. These malicious addition and modification of circuits done by the intruders are commonly referred to as hardware Trojan (HT). Currently, power based side channel analysis is one of the most promising techniques in detecting HT. Due to elevated process variations, especially random variation as process technology nodes are rapidly scaled down; obtaining high detection sensitivity using power based side channel analysis is becoming a very challenging task. To overcome this challenge, in this thesis, initially, the impact of random variation in detecting HT is analyzed. To accomplish this task, Mote Carlo simulation environment is established for analyzing dynamic power distribution due to random process variation. Based on the analysis of dynamic power variation, a new HT detection condition is proposed considering random process variation. Therefore, we propose a new HT detection method ANP (Arbitrary neighboring test pattern pair comparison) based on the new HT detection condition. Finally, detectability is evaluated by injecting two type of HTs in benchmark circuits. ANP shows relatively high detectability (ex:100%) for medium size HT (0.3-0.4% to a whole circuit) and 24%-100% for a small HT (0.07%-0.09% for some circuits) for moderate random variation (0-1% standard deviation for delay variation) and still show some possibility of detection for elevated random variation (2 - 5% standard deviation for delay variation).