Recently, Thin Film-Transistors (TFTs) have emerged as devices that exhibit higher mobility compared to amorphous silicon ones. The ZnO-based TFTs technologies have already been widely used in large-area displays for being fabricated on plastic substrates in low temperature, resulting in low production costs. However, the ZnO-based TFTs technologies have not been used for the processors yet. With the rapid development of this fabrication technology in integrated circuits, processor implementation using ZnO-based TFTs is being studied at NAIST. Using an inkjet printing technology, an integrated circuit can be printed on new material sheets. However a challenging issue for making this technology practical is that the incidence of circuit malfunctions is higher than that of conventional silicon materials. Most smart-phones currently use 32-bit ARM processors, and have many applications available. However, such 32-bit processors require a large number of transistors in the processors. High performance processor that has large transistor numbers leads large scales. The larger transistors number of a processor leads to more chances of failures for implementing processors on new materials. Before the device technologies becoming mature enough, it is essential to design a simple architecture processor that has small transistor numbers. To solve this issue, processors using smaller bits (e.g., 8 bits) are required for decreasing the incidence of malfunctions. In the existing 8-bit processors, the today 32/64-bit applications cannot be executed on such 8-bit processors. In addition, the performance of 8-bit processors existing is not efficient today as most of therecent software is implemented for 32/64-bit processors. For these reasons, an 8-bit processor that can efficiently execute 32-bit ARM applications has been proposed in our previous work. The existing 8-bit processor (6502 CPU) had been compared with the 8-bit ARM emulation-oriented processor (EMIN CPU). However, the 6502 CPU is not designed for ARM emulation. The merits of the 6502 CPU emulator are that the zero page memory space has been implemented as registers. This merit should be retained to reduce the area of processors. On the other hand, the 6502 CPU takes loops to perform 32-bit ARM instruction load and store. In addition, N-way switch needs a lot of steps to perform instruction decode. To improve the demerits of the 6502 CPU for ARM emulation, we propose a new processor named 6502 plus Alpha that is specialized for ARM
emulation. The 6502 plus Alpha extends the address bus from 16-bit to 24-bit that can access the 32-bit ARM program counter. A new address mode named word has been added with load and store instruction to perform the 32-bit ARM instructions without loops. The Y index register is not only the loop counter but also keeps the ARM register number in the 6502 plus Alpha CPU. The instructions LDYR and STYR are added for loading and storing the ARM register data without using indirect addressing processes. The table branch instructions are added to improve the performance of ARM instruction decode. The processor status register is re-designed to facilitate ARM emulation. The ASL (Arithmetic shift left) and LSR (Logic Shift Right) instructions have the immediate address mode in the 6502 plus Alpha CPU. This thesis presents the results of dynamic steps, static steps, and the area of the 6502 plus Alpha CPU compare with those of the 6502 CPU. Finally, the ADP (Area-Delay Product) is used to evaluate the area-time trade-off. It is found that the ADP of the 6502 plus Alpha CPU
on average is 68.5% of that of the 6502 CPU. This indicates that the 6502 plus Alpha CPU is a better choice for ARM emulation against 6502 CPU.