Parallel Path Delay Fault Simulation for Multi/Many-Core Processors

Yussuf Ali (1251130)


The path delay fault model is a useful but complex delay fault model. The information about sentitizable paths is very useful for application like pattern validation or diagnostics. Due to the exponential growth of paths inside the circuit acceleration is needed. With multicore hardware this acceleration can be achieved.

For implementation of the algorithm OpenCL is used. With the help of OpenCL parallel programs can be developed in a platform independent high level language. Programs developed in OpenCL can run on a variety of multi-/many-core hardware. The simulator exploits two levels of parallelism; bit-parallel operations are used at every stage of the simulator in addition to multiple threads which simulate the same design but for different pattern. Three different versions of the algorithm were developed. They were benchmarked against a commercial tool. Even though the commercial tool just performed a logic simulation with two pattern sets all developed algorithms were much faster then the commercial tool.

The sequential version of the algorithm is 3x faster and the parallel versions are up to 24x times faster then the commercial tool. The fastest parallel version is able to simulate 53248 patterns in less then 2 seconds.