Power Analysis and FPU Placement Modeling for FU Array Accelerator

Devisetti Venkata Rama Naveen (1051136)

With the increasing ability to place more transistors in one chip along the development of semiconductor process technologies, many architectures have been explored to well balance three important aspects, which are performance, power consumption, and programmability. In my laboratory, previously LAPP (Linear Array Pipeline Processor) was proposed to balance all the three important aspects. Specifically, loop kernel codes are mapped fixedly onto a minimal number of Functional Units (FUs) inside the FU array. The loop execution is fully accelerated by exploring the parallelism between loop iterations. In this presentation, I am going to propose a power reduction model for LAPP to consume the minimum required power, by using gating technologies. Compared to the many-core processor of same area, an LAPP-simulator based estimation indicates that LAPP can achieve better power efficiency. In order to extend the range of applications working on LAPP, I also propose different placement models to place Floating Point Units on LAPP. The evaluation results show that by placing an FADD and FMUL unit in each stage, it is possible to fulfill the FP resources for most benchmarks.