Studies on Power-Aware Wrapper Design for Multi-Clock Domain Cores Using Clock Domain Partitioning

Yu, Thomas Edison Chua (0551141)

The rapid advancement of VLSI technology has made it possible for chip designers and manufacturers to embed the components of a whole system onto a single chip, called System-on-Chip or SoC. SoCs make use of pre-designed modules, called IP-cores which enable faster design time and quicker time-to-market. Furthermore, SoCs which operate at multiple clock domains and very low power requirements are being utilized in the latest communications, networking and signal processing devices. As a result, the testing of SoCs and multi-clock domain embedded cores under power constraints has been rapidly gaining importance. For this research, a novel method for designing power-aware test wrappers for embedded cores with multiple clock domains is presented. By using bandwidth conversion, multiple shift frequencies and gated clocks, the proposed method improves upon previous methods which require that test data be shifted into all scan-chains concurrently. Furthermore, the partitioning of clock domains into smaller sub-domains is allowed which gives greater flexibility when determining an optimal test schedule under very tight power constraints. A heuristic 3-D bin packing algorithm is also proposed to determine the optimal wrapper architecture and test schedule while minimizing the test time under power and bandwidth constraints.