Studies on False Path Identification Using Assignment Decision Diagrams
Vorayos Thongtan(0551139)
Nowadays as a consequence of the increasing speed of integrated circuits, the delay fault testing which is to ensure that the circuits meet the timing constraint is playing a vital role in the semiconductor industry. Path delay fault testing is one of the most important delay fault models because it is considered to be closest to the ideal model for delay defects. In order to ease the test generation process for path delay fault testing, circuit designers use design-for-testability (DFT) techniques, e.g. scan techniques. These techniques require some extra hardware. In return for easing testing, the DFT techniques lead overtesting which induces yield loss. Overtesting happens when untestable path delay faults that never affect the performance of the circuit in normal operation have been tested. Moreover, a large number of path delay faults are untestable. To reduce overtesting, it is necessary to identify the untestable path delay faults. However, the number of paths in a circuit at gate level is extremely large and handling all the path delay faults in the circuit is impractical. Therefore, in this thesis, the algorithm for identifying false paths by using the information from register transfer level (RTL) is presented. The methodology uses a unified RTL circuit representation, called assignment-decision diagrams (ADDs). The algorithm does not require a clear separation between controller and datapath in the circuit, which is suitable for current designing trends. Experimental results show that the proposed false path identification method can identify many faults as untestable.