Software-Hardware Co-design and its Evaluation Framework for Decimal Multiplication

Riaz-ul-haque Mian


The binary number system cannot accurately represent many common decimal values and binary arithmetic causes some unexpected errors that changes the actual value of the exact result. Due to the shortcomings of binary floating-point arithmetic, many applications involving decimal data are forced to perform their arithmetic either entirely in software or decimal floating-point hardware. Decimal arithmetic using software is slow for very large-scale applications. On the other hand, when hardware is employed, extra area overhead is required. A balanced strategy with software-hardware co-design can provide several Pareto points to the development of embedded systems in terms of hardware cost and performance. The presentation of this study starts with this background of decimal computing. However, there is no integrated platform available to develop and accurately evaluate co-design-based decimal arithmetic. In this study, first, an integrated open-source framework is proposed to design and evaluate such codesign-based decimal multiplication. The framework can realize cycle-accurate analysis for performance as well as hardware overhead for co-design solutions for decimal multiplication. In the evaluation framework, new customized binary instruction and decimal oriented instructions supported by an accelerator to design and evaluate decimal multiplication are developed. The framework customizes the RISC-V ecosystem, IBM decNumber library, and test database for functional and performance verification. Besides the customization, a set of programs is developed to manage the framework and generating the necessary test program. The presentation contains details of the proposed framework and its evaluation process.

Furthermore, as there is no software-hardware co-design-based decimal arithmetic solution exists, this presentation then includes the proposed methods for decimal multiplication. The proposed methods are compliant with the IEEE 754-2008 standard for decimal floating-point arithmetic and combinations of software and hardware.

Finally, using the proposed framework, the decimal multiplication process is analyzed and a new Pareto point for software-hardware co-design-based decimal multiplication is also proposed. Analysis in different platforms, including the proposed integrated evaluation framework, reveals that the proposed methods provide several Pareto points for decimal multiplication solutions. The discussion ends with this analysis and results with futrure vision. In this study, decimal multiplication is considered for codesign, because multiplication is one of the most important, primitive, complex-to-implement, and frequently used decimal arithmetic.