Embedded memory is extensively being used in System-on-Chips (SoCs), and is rapidly growing in size and density. It contributes to SoCs to have greater features, but at the expense of taking up the most area. Due to continuous scaling of nanoscale device technology, large area size memory introduces aging-induced faults and soft errors. They manifest in field, which is a concern as causes of errors. Hence, reliability of memory is crucial to overall reliability of SoCs.
Existing techniques used for memory reliability includes 1) in-field self-test and repair, which performs memory test while system is in operation in order to identify faulty elements, as well as peforming repair by replacing faulty elements with spare elements, and 2) Error Correction Code (ECC), which is now a predominant feature in almost all SoCs, wherein extra information is used in order to maintain integrity of data elements. Recent techniques have combined these two approaches, and it gives a synergistic effect in maintaining memory reliability.
In this thesis, the combination of self-repair and ECC is explored further so that it can be efficiently used to perform memory repair. Two architectures are proposed as solutions that enhances reliability further. The first architecture shows a reliability problem that can occur from the combination of repair and ECC, and an adaptive strategy is implemented to address this problem. The second architecture explores how aging makes memory more susceptible to errors, and an aging-aware strategy is presented on how to mitigate the effects of aging. Experimental results show that both architectures further enhances reliability.