| 芳賀 陸雄 | D, 中間発表 | 情報セキュリティ工学 | 藤本 大介 | 中島 康彦 | 林 優一 | 井上 美智子 | |
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title: The study on Design Methodology of Physical Attack-resistant Post-quantum Cryptographic Hardware for Resource-restricted Devices
abstract: Research and development is underway on quantum computer resistant cryptography (PQC), which is secure against quantum computers. Compared to conventional public-key cryptography, PQC requires more complex computations, which increases the cost of implementation. Although there are no major problems on the server side, where computational resources are abundant, implementing PQC in resource-restricted devices such as edge-node devices, which are the counterpart of encrypted communication, is difficult to improve energy efficiency due to the small area and increased processing time caused by the increased computational complexity due to the large values to be handled. In addition, the threat of side-channel attacks (SCA) has been reported, as attackers are able to approach devices that are installed far from the administrator, such as edge node devices. Several methods have been proposed to defend against SCA, but their overhead would significantly reduce energy efficiency. Therefore, the purpose of this study is to show that, against the increase in implementation cost due to the increase in modulus size of modular operation in the transition to PQC, increasing the number of parallelisms of modular multipliers by value splitting can lead to improved energy efficiency and SCA resistance. This will lead to an SCA-resistant HW design of PQC for resource-restricted devices. We propose a small area and energy efficient design method for large modulus parallel modular multipliers and report a 34% improvement in energy efficiency compared to applying previous studies. language of the presentation: Japanese 発表題目: 資源制約のある機器における物理攻撃耐性を有した耐量子計算機暗号HW設計法に関する研究 発表概要: 量子計算機に対しても安全な耐量子計算機暗号（PQC）に関する研究開発が進められている。 PQCは従来の公開鍵暗号技術と比べてより複雑な計算処理を要するため実装コストが増大している。 計算資源が豊富なサーバーサイドでは大きな問題は無いが、暗号化通信の相手となるエッジノードデバイスのような資源制約のある機器へのPQCの実装は、扱う値の大きさから小面積化や計算量の増大による処理時間の増加によりエネルギー効率の向上が難しくなっている。 また、エッジノードデバイスのような管理者から離れた位置に設置される機器には攻撃者が接近可能なためサイドチャネル攻撃（SCA）の脅威が報告されている。 SCA対策の手法は複数提案されているが、そのオーバーヘッドによりエネルギー効率が著しく低下する可能性がある。 そこで、本研究ではPQCへの移行で剰余演算の法サイズが増加したことによる実装コストの増大に対して、値の分割による並列剰余乗算器の並列数の向上がエネルギー効率の向上とSCA耐性の向上に繋がることを示すことを目的とする。 これにより、資源制約のある機器へのSCA耐性を有したPQCのHW設計の実現を目指す。 本発表では、大きな法における並列剰余乗算器の小面積かつ高エネルギー効率な設計法を提案し、先行研究を適用した場合に比べてエネルギー効率が34%改善する見積が得られたことを報告する。 | |||||||
| LI MINGYANG | D, 中間発表 | コンピューティング・アーキテクチャ | 中島 康彦 | 林 優一 | 張 任遠 | KAN Yirong | PHAM HOAI LUAN |
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title: Implementation of a Spiking Neural Network Accelerator with Structured Sparse Connections for Edge Computing Applications
abstract: The booming development of IoT applications makes low-cost edge computing increasingly important. Spiking Neural Network (SNN) has shown great potential for low-power operation on battery-powered devices. We propose a fully parallel reconfigurable SNN accelerator. In contrast to conventional fully connected and irregular sparse network topologies, structured sparse synaptic connections significantly reduce neuron computation and weight memory costs, implement SNN in fully parallel without significantly reducing accuracy. For more complex tasks, the accelerator also supports configuration as the spiking convolutional neural network mode. By exploring training, quantization techniques, dataflow management, hardware design and optimal settings of the proposed accelerator, we aim to provide a low-power, highly parallel accelerator platform for power and cost constrained devices, implement more intelligent and efficient edge computing application. language of the presentation: English | |||||||
| TANG HAOYU | D, 中間発表 | コンピューティング・アーキテクチャ | 中島 康彦 | 林 優一 | 張 任遠 | KAN Yirong | PHAM HOAI LUAN |
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title: Enhancing Hardware Resilience of Hyperdimensional Computing via Dynamic Stochastic Encoding
abstract: Brain-inspired Hyperdimensional computing (HDC) is a computational framework that emulates neural activity within a high-dimensional space. In this paradigm, data points are encoded into high-dimensional vectors, termed hypervectors (HVs), for structured information representation. The encoded training HVs are used to generate class HVs under a well-defined set of operations. Testing HVs are encoded in the same way as training HVs and are used to perform pattern classification by checking similarity to the class HVs. Although great promise of HDC, it requires the preprocessing of complex data features. Therefore, an efficient and robust encoding approach is crucial for practical HDC implementation. In this work, we propose a novel encoding approach and hardware implementation by integrating Stochastic Computing (SC) to HVs. SC is a paradigm aimed at encoding and computing using probability-based representations. Our approach involves quantizing feature values into several levels by determining the maximum and minimum values and then representing them using probability density. Finally, after bundling, a binarized hypervector is obtained. This approach, which combines dynamic random stream-based stochastic encoding, replaces the need for pre-stored seed hypervectors (huge memory consumption), enabling more efficient and scalable hypervector generation in varying environments. And it also enhances the robustness of hypervectors and enables a hardware-friendly implementation of HDC while ensuring spatial correlation between adjacent positions. Moreover, it significantly reduces overhead through binarized HVs or even binarized models. language of the presentation: English | |||||||