| 野村 武司 | M, 2回目発表 | コンピューティング・アーキテクチャ | 中島 康彦, | 林 優一, | 中田 尚, | TRAN THI HONG, | 張 任遠 |
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title: An Energy Efficient Stochastic+Spiking Neural Network
abstract: Spiking Neural Networks (SNNs) have won great attentions due to their inherent potential to achieve low-power consumption beyond the limitation of conventional Deep Neural Networks (DNNs). In general SNN theory, input data and layer-by-layer communication can be carried out by various appearance-features of spikes including density, distribution, rate, and timing. When SNNs are implemented onto hardware, complex spike representations are expansive in the sense of hardware resource and processing time. In this research, we develop Stochastic+Spiking Neural Network(SSNN) and its hardware implementations without any additional spike-coding mechanism. By performing the input layer through stochastic computing, the spike coding is avoided to greatly reduce the hardware utilization and power consumption. language of the presentation: Japanese | |||||||
| NGUYEN VAN TINH | D, 中間発表 | コンピューティング・アーキテクチャ | 中島 康彦, | 林 優一, | 中田 尚, | Tran Thi Hong, | 張 任遠 |
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title: High Speed and Compact Stochastic Deep Neural Networks employing Exponential Transform
abstract: Stochastic Computing-based Deep Neural Networks (DNNs) Design has received extraordinary attention due to the low-power area-efficient hardware implementation. However, the combination of Stochastic and Conventional Computing in DNNs leads to reduction of the hardware-efficiency of Stochastic Computing. In this work, we overcome this limitation by presenting a novel algorithm that allows Stochastic Computing-based Deep Neural Network is implemented with high speed by employing exponential transform. By performing simple hardware-friendly AND gates on exponential transform-based stochastic adders and a single JK-FF-based activation function, complex calculations of neural synapses can be realized very efficiency. The measure power on a FinFET fpga 16 nm Zynq UltralScaled + MPSoC ZCU 102 is 2.28 W, and our architecure yields 80% reduction in hardware efficiency to compared with integral stochastic DNNs. Simulation in the example of the Fashion-MNIST datasets show that such networks can approach the performance of floating point computation. A mean MNIST classification accuracy is 92,05% (which is 4.05% lower than 32 bit floating point) using a three-layer sparse MLP. The correctness of the circuit was verified on a real hardware platform (ZCU 102). language of the presentation: English. | |||||||
| TRAN THI DIEM | D, 中間発表 | コンピューティング・アーキテクチャ | 中島 康彦, | 林 優一, | 中田 尚, | Tran Thi Hong, | 張 任遠 |
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title: Primary Visual Cortex Inspried Feature Extraction Hardware Model
abstract: Reflecting various physical phenomena of the primary visual cortex (V1) in hierarchical approaches has become prevalent over the years when the semiconductor miniaturization reaches its limit. In this research, we propose a V1 hardware model to extract features. Our architecture with the edge, slit, left-right parallax, XY movement direction, and approach detection functions are partially mimicked from V1. The fundamental model is the sum of absolute differences algorithm and the AND function. Convolutional neural networks (CNNs) have dominated a range of applications, from advanced manufacturing to autonomous cars. The growth of network size that increases with computation time and memory consumption is the primary issue. Due to the large input size, the first few convolutional (CONV) layers in the CNN model generally contribute to a high cost in computation time, making these layers' latency is the second challenge. To address these challenges, we use the slit function of the V1 model to extract feature maps and reconstruct the first few layers on CNNs. A simple topology that demands no parameters during the training phase replaces the first layer on CNNs. Total multiply-accumulate units (MCAs) are eliminated on the first layers in way reconstruction with our approach. language of the presentation:English | |||||||