| 西山 輝 | M, 2回目発表 | 情報セキュリティ工学 | 林 優一, | 岡田 実, | 藤川 和利, | Kim Youngwoo |
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title:Validation and Analysis of Transmitted Data Error caused by IEMI induced in the Input/Output Circuit Power Distribution Network
abstract: Information devices operating in physical space connected to cyberspace, such as IoT devices, have communication channels that connect the two spaces. Since these communication channels are isolated from cyberspace, security functions such as encryption and error detection/correction are not implemented, the communication channels are vulnerable to external noise. Among various external noises, an intentional electromagnetic interference (IEMI) can easily induce EM noises to the information device. If the noise is induced in the printed circuit board (PCB) level input/output circuit (I/O) power distribution network (PDN) due to the IEMI, it will have significant impacts on the communication channels causing data and commands error. However, the IEMI induced in the I/O PDN causing data error has not been discussed. Therefore, in this study, the impacts of the IEMI induced to the I/O PDN of the information devices generating errors in the transmitted data are verified by the experiment. Induced noise in the I/O PDN degraded the signal integrity of the communication channel significantly, which generates errors in the transmitted data. It is extremely important to estimate and evaluate possible IEMI threats on the PCB level I/O PDN in the early design stage. Therefore, an accurate simulation method that can estimate the impacts of induced noise in the I/O PDN is proposed and validated. Using the proposed simulation method, impacts of the induced noise in the I/O PDN on signal degradation and data error are analyzed. Finally, the final goal of this study is to establish the design guides which increase immunity against IEMI to the information devices connected to cyberspace. language of the presentation: Japanese | ||||||
| 上田 葵 | M, 2回目発表 | ディペンダブルシステム学 | 井上 美智子, | 浦岡 行治, | 大下 福仁, | 新谷 道広 |
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title: Measurement of Threshold Voltage Shift of SiC MOSFETs under Actual Operation
Owing to the increasing demand for highly efficient usage of electric power, high-efficient power conversion circuits using SiC (silicon carbide) MOSFETs have been expected. Compared to the conventionally used silicon, SiC devices can tolerate high-voltage and high-temperature operations with low power loss. However, it has been pointed out that SiC MOSFETs have problems in long-term reliability. In particular, the detailed atomic origin of bias temperature instability (BTI) has been still heavily debated, and the currently widely adopted BTI measurement method has a problem that does not consider the actual operating environment. In this considering the actual operating environment. We measure the temporal change of threshold voltages of commercially available SiC MOSFETs and silicon MOSFETs, and then we discuss their physical mechanisms based on the measured data. language of the presentation: Japanese 発表題目: 実動作環境を考慮したSiC MOSFETのしきい値電圧シフトの測定 電力の高効率利用に対する需要の高まりから，SiC（炭化ケイ素）MOSFETを用 いた電力変換回路が期待されている．SiCは，従来から用いられているSiと比 較して，絶縁破壊電界強度，飽和電子速度，熱伝導等の特性が優れている．一 方で，SiC MOSFETは長期信頼性に課題があることが指摘されている．特に，バ イアス温度不安定性（Bias Temperature Instability，BTI）は，未だ物理的 要因が明らかになっていない上，現在広く採用されているBTI測定手法は実動作環 境を考慮していない課題がある．本研究では，実動作環境を考慮した高精度な BTIの測定を提案する．市販のSiC MOSFETおよびSi MOSFETのしきい値電圧を測定 し，その物理的要因を考察する． | ||||||