| 倉地 亮介 | M, 2回目発表 | ソフトウェア設計学 | 飯田 元, 井上 美智子, 市川 昊平, 高橋 慧智 |
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title:Investigation for test code reuse using similar code detection tool
abstract: In order to reduce test code creation costs in software development, the use of automatic test code generation tools is progressing. However, there is a problem that makes it difficult for developers to maintain the generated test code by existing tools because it is not based on the creation process and intention of the target code. We believe that a automated test generation tool by reusing existing tests between similar codes is necessary as a solution. In general, reuse of existing tests is considered to be able to use highly readable code and reliable code.On the other hand, reusing source code is considered a difficult task because it is necessary to fully understand and use the target source code. This is also considered difficult for reusing test code. Therefore, it is important to clarify the types of test code that can be reused between similar code. In this study, we classify similar code pairs in Java projects according to the presence of test code. Based on the results, the percentage of similar code pairs that are reuse candidates in the project and similar code pairs We investigated the relationship between the similarity of test and the similarity of test code. language of the presentation:Japanese | |||
| 岩本 淳 | M, 2回目発表 | コンピューティング・アーキテクチャ | 中島 康彦, 井上 美智子, 中田 尚, Tran Thi Hong, 張 任遠 |
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title: Evaluation of a Chained Sysolic Array with High-Speed Links
abstract: A paradigm shift toward edge computing infrastructures that prioritize small footprint and scalable/easy-to-estimate performance is increasing. The former improves the yield ratio and the latter eliminates the margin for performance guarantee. Consequently, both of these directions reduce the cost of hardware. In this research, we propose a chained systolic array that connects small systolic array chips with peer-to-peer AXI interfaces, and evaluate the scalability of several types of topologies such as star and tree with some models implemented on FPGAs conected by aurora links. As a result, we found the star structured 4-chips configuration provides maximum 2.8 times performance of 1-chip configuration. In addition, we found that current implementation with aurora link (15Gbps) is insufficient to get enough scalability as expected in the tree and daisy chain configuration. language of the presentation: Japanese | |||
| 新谷 隆太 | M, 2回目発表 | コンピューティング・アーキテクチャ | 中島 康彦, 井上 美智子, 中田 尚, Tran Thi Hong, 張 任遠 |
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title: Study of compression technology for communication efficiency in distributed CNN
abstract: Since the amount of calculation required for the inference processing of the neural network is large, it is processed not by a location getting data but by a server having abundant calculation capacity in the data center. However, due to the recent increase in IoT devices, it increases in power consumption of servers and network switches and occurs traffic congestion. Therefore, we assumed a distributed neural network model using edge computing to be implemented in the future. By processing a part of the convolution layer on the edge side, the amount of information to be transferred becomes smaller than the sensor data. Compression processing was executeed before transferring middle data, and changes in file size and object recognition accuracy after compression were evaluated. As the compression method, We adopted H.265 / HEVC, which are one of the video compression standards, bzip2 and run length compression and zero value compression. We also investigated the processing time required for encoding and decoding. As a result, when using HEVC compression in the 5th pooling layer in VGG16, it was found that the recognition accuracy was reduced to 0.17% with a compression rate of 2.99%. language of the presentation: *** English or Japanese (choose one) *** | |||