| AHMED FOISAL | D, 中間発表 | ディペンダブルシステム学 | 井上 美智子, 中島 康彦, 大下 福仁, 新谷 道広 |
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Title: Recycled FPGA Detection Using FPGA Fingerprinting
Abstract:Presently, recycled FPGA is now a great concern in the critical applications such as automobile, medical and communication systems due to some reliability and security issue. To detect recycled FPGA, existing research methods apply fingerprint of the golden FPGAs where needs a large number of measurement circuits and feature vectors. However, lots of feature vectors considerably increase database size and causing the curse of dimensionality problem in the machine learning based recycled FPGA detection. To address these potential problems, we propose two low-cost methods of recycled FPGA detection using Compressed Sensing (CS) and with-in die (WID) variation modeling technique. We found 99.6% database reduction using WID based recycled FPGA detection method whereas 80% measurement reduction is obtained at the best case using the CS technique. Future work involves with golden database free that will be a more efficient way of recycled FPGA detection. Language of the presentation: English | |||
| MIAN RIAZ-UL-HAQUE | D, 中間発表 | ディペンダブルシステム学 | 井上 美智子, 中島 康彦, 大下 福仁, 新谷 道広 |
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Title: Decimal Multiplication Using Software Hardware Co-Design
Abstract: Decimal arithmetic through software is slow for very large scale application, while it needs extra area overhead through hardware. A balanced strategy with software-hardware co-design solutions for decimal computation can provide several Pareto points to development of embedded systems in terms of hardware cost and performance. Design and accurate evaluation of such co-design solutions are challenging. We propose several methods for decimal multiplication using a combination of software and hardware that can reduce the execution time by 24%-81% compared to a standard software library with 25%-94% less hardware compared to an area efficient full decimal multiplier. We also propose an opensource based evaluation framework to accurately evaluate such a co-design method for decimal computation. Language of the presentation: English | |||
| TATI ERLINA | D, 中間発表 | コンピューティング・アーキテクチャ | 中島 康彦, 井上 美智子, 中田 尚, TRAN THI HONG, 張 任遠 |
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title: *** Low Energy and High Speed VLSI Implementations of Time Based Stochastic Computing ***
abstract: *** In the growing concern of computation efficiency as the result of the thriving deployment of Internet of Things (IoT) and the slowing down of Moores Law, stochastic computing (SC) has been considered as one of promising solutions. This due to the low cost hardware and error tolerance of SC implementation. However, to achieve sufficient accuracy, conventional SC needs to be represented by a long bit streams, thus, increasing processing time and energy consumption. Therefore, we have designed a time-based stochastic computing (TBSC) circuit that outperforms the original TBSC circuit; using less number of transistors (~14%) and consuming less energy (~66%) while producing output with comparable accuracy. In order to reduce overall processing time and energy consumption further, we are investigating to leverage multiple signal features to enable a denser representation of SNs as well as its operation result in a single wire. This rich representation of SNs is expected to solve real world problems such as hardware implementation of neural network. *** language of the presentation: *** English *** | |||