| 上岡 真也 | 1451017: M, 2回目発表 | 井上 美智子，中島 康彦，大下 福仁，米田 友和，大和 勇太 |
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Title: Background Sequence Generation for Neighborhood Pattern Sensitive Fault Testing in Random Access Memories
Abstract: The Neighborhood Pattern Sensitive Fault (NPSF) is a widely discussed fault model for memories, which occurs when a memory cell is influenced by a certain pattern of its neighborhood cells in the memory. We present a method to automatically generate a background sequence to detect given NPSFs. The proposed method formulates the problem of finding the background sequence as an integer linear programming problem. Experimental results show that the proposed method can generate the background sequence with a reasonable CPU runtime. language of the presentation: Japanese | ||
| 川崎 真司 | 1451037: M, 2回目発表 | 井上 美智子，中島 康彦，大下 福仁，米田 友和，大和 勇太 |
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title: Delay fault emulation framework on FPGA
abstract:In order to satisfy reliability requirements, understanding the behaviour of a LSI with timing failure is important.Fault injection is used for such a purpose. Since software approaches are quite slow, emulation-based approaches to accelerate the fault injection process are needed. In this presentation, I will present an emulation-based approach that can efficiently emulate the real delays of target circuit produced for ASIC technology on FPGA, and discuss the performance of proposed method. language of the presentation:Japanese | ||
| 里中 沙矢香 | 1451053: M, 2回目発表 | 井上 美智子，中島 康彦，大下 福仁，米田 友和，大和 勇太 |
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title:Built-In Self-Test with Combination of Weighted Random Pattern and Reseeding
abstract:Modern complex designs demand more reliable and effective testing with short test time and low hardware overhead. Built-in self-test (BIST) is a cost effective solution to test today's complex designs. In order to improve the effectiveness of BIST, weighted random pattern testing and LFSR reseeding have been discussed. We present a method of cobining the weighted random pattern testing and LFSR reseeding to achieve high fault coverage with short test time and low overhead. I will present current research progress and future plan. language of the presentation: Japanese | ||
| 水谷 早苗 | 1451102: M, 2回目発表 | 井上 美智子，中島 康彦，大下 福仁，米田 友和，大和 勇太 |
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title:A Switching-Distribution-Aware IR-Drop Estimation Method
abstract:With shrinking feature size of LSI circuits, delay testing has become important. However, delay variation due to IR-Drop may affect test quality. Although it is necessary to estimate IR-drop for each pattern and screen out problematic patterns a priori since the amount of IR-drop depend on a pattern, IR-drop analysis based on circuit simulation is time-consuming. To quickly estimate IR-drop, an method exploiting high correlation between whole circuit power and per-cell IR-drop has been proposed. However, estimation accuracy may decrease if the pattern has spatially lopsided distribution of signal switching. In this work, we propose an accurate IR-drop estimation method being aware of spatial distribution of switching. language of the presentation:Japanese | ||