ゼミナールI講演

日時: 平成21年7月6日(月)3限 (13:30 -- 15:00)
場所: L1

講演者: Krishnendu Chakrabarty (Duke University)
題目: Delay-Testing Techniques for Nanoscale Integrated Circuits: From Gross-Delay Defects to Small-Delay Defect
概要: Timing-related defects are major contributors to test escapes and in-field reliability problems for nanoscale integrated circuits (ICs). Timing problems are caused by gross delay defects, resistive shorts and opens, as well as by delay variations induced by crosstalk, process variations, and power-supply noise. The complexity of today’s ICs and shrinking process technologies are also leading to prohibitively high test data volumes. As a result, the 2007 ITRS document predicted that the test data volume for integrated circuits will be as much as 38 times larger and the test application time will be about 17 times larger in 2015. The speaker will first present an overview of delay-testing techniques used today in industry. Basic concepts such as fault models, design-for-testability, and test-application methods will be covered. Next, the speaker will present emerging test techniques for defect screening, which uses the method of output deviations for handling unmodeled faults. A new gate-delay defect probability measure will be defined to model delay variations and erroneous behavior for nanometer technologies. This approach requires significantly lower computational complexity and lower pattern counts (thereby less test data volume and test time), and it excites a larger number of long paths compared to commercial timing-aware test-generation tools. The speaker will present results for benchmark and industrial circuits to highlight that, with lower pattern count, the proposed method provides more effective coverage ramp-up than timing-aware test generation.
講演者紹介: Krishnendu Chakrabarty教授は、1995年に University of Michigan, Ann ArborでPhD取得後、Boston UniversityでAssistant Prof., Duke UniversityでAssociate Prof.を経て、2007年からDuke University, Dept,. Electrical and Computer Engineeringで教授。計算機工学における分野で、特にシ ステムオンチップ(SoC)の設計とテスト、バイオチップの設計 自動化、分散センサーネットワーク、などの分野で重点的に研究を 行っている。これまでに200編を超える論文を発表、IEEE Trans. on CAD, IEEE Trans. on VLSI Systemsなどの編集委員、多くの国際会 議の実行委員、プログラム委員長、などを歴任。39歳の若さで IEEE Fellow の称号を得ている(1968年生)。親日派で、日本には 毎年のように訪問している。今回、日本学術振興会外国人招聘研究 者(受入研究者:藤原)として、また奈良先端大外国人招聘教授と して、本学を訪問中。

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