ゼミナールI講演

日時平成 18年 11月 1日(水) 3限 (13:30 -- 15:00)
場所L1
講演者Yu Hu
所属 Institute of Computing Technology, Chinese Academy of Sciences
講演題目 Design-for-Testability of Integrated Circuits: Principles and Case Studies
概要
Testing is a key aspect of integrated circuits development, because of its cost and impact on final product reliability. Along with the increasing circuit size and shrinking feature size, design-for-testability (DFT) plays a more and more important role to improve test quality and reduce test cost. In this talk, firstly we will introduce the principles of DFT, including fault models, automatic test pattern generation, scan design and memory built-in-self-test, and then we will give cases of DFT for high performance microprocessors such as CELL from IBM/Toshiba/Sony and Alpha 21364 from Compaq/HP.
担当教官・司会:藤原秀雄

ゼミナールI,II予定ページへ戻る

平成18年度ゼミナールI担当