ゼミナールI講演
日時平成 18年 6月 19日(月) 4限 (15:10 -- 16:40)
場所L1
講演者Danella ZHAO
所属 Center for Advanced Computer Studies, University of Louisiana at Lafayette, Assistant Professor
講演題目 An Integrated Framework for Concurrent Test and Wireless Control in Complex SoCs
概要
System-on-chip (SoC) is evolving as a new design style, where an entire system is built by reusing pre-designed, pre-verified IP (intellectual property) cores. Embedded with numerous heterogeneous and complex IP cores, a SoC can be viewed as an interconnected network of various functional modules. This new design style shortens time-to-market while meeting various design requirements, such as high performance, low power, and low cost, compared to the traditional system-on-board (SoB) design. In the meantime, however, embedded core-based SoC test becomes a challenging task due to IP protection. In particular, there are three major issues to be addressed in SoC test: (1) a test access path needs to be constructed for each core to propagate test stimulus and collect test responses, (2) one needs to partition test resources and schedule IP cores to achieve maximum parallelism, and (3) a test control network is needed to initialize different test resources used in the test application and observe the corresponding test results at appropriate instants. In this talk, I mainly present two research issues addressed in our group: integrated testability design and optimization of SoC test solutions, and on-chip wireless test control network design. I first introduce a general test model for SoC testability analysis, test scheduling, and test diagnosis. I then describe several proposed test scheduling algorithms with the consideration of various test constraints such as resource sharing, power dissipation, and fault coverage, and develop an integrated framework that combines wrapper design, test access mechanism (TAM) configuration, and test scheduling. Using the ＜Radio-on-Chipｃ technology, I introduce a novel test control network to transmit control signals chip-wide by RF links. I will present three types of wireless test control architectures, i.e., a miniature wireless LAN, a multihop wireless test control network, and a distributed multihop wireless test control network. Under the multilevel tree structure, the system optimization is performed on control constrained resource partitioning and distribution. Several challenging system design issues such as RF nodes placement, clustering, and routing, are studied along with integrated resource distribution and test scheduling. Cost oriented optimization technique is developed which addresses several highly interdependent design issues to achieve the minimum overall testing cost.
備考:
担当教官・司会:藤原 秀雄 教授
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