Test Response Compaction for Error Detection and Diagnosis
概要
Testing of VLSI circuits is challenged by the increasing
volume of test data that add constraints on tester memory and impact
test application time substantially. Test response compactors are
commonly used to reduce that test volume by orders of magnitude.
In this presentation, new compaction schemes will be introduced to
address two problems: 1) the masking of errors caused by unknown values
in the test response and 2) the identification of errors from the
compacted response. The properties of the compactors will be derived and
their performance will be evaluated through simulation results.