We outline in this context research aimed at extracting and utilizing test-related information at higher levels than the traditional gate-oriented approaches. As designs get ever larger and time-to-market constraints keep shrinking, ever higher levels of design entry and automated synthesis become prevalent. While high level synthesis tools are currently commercially available, none of them offer the ability to consider test during synthesis. We outline a "high level test synthesis system", capable of automatically generating self-testable ASICs. Complex designs such as microprocessors need to handle test concerns nowadays at RT levels of abstraction and possibly higher, as gate-level ATPG, test analysis and DFT tools are unable to cope with the complex tasks imposed by such designs. We outline "RT level test analysis & translation" approaches particularly oriented towards processor designs. While processor and other large complex designs necessitate RT level test tools, concise domains such as "digital signal processing test" can benefit from precise analysis to extract rapid methods operating at higher functional levels both for self-test and for online test. We outline such functional methods for redundancy extraction, alleviation of pseudorandom test resistance, LFSR selection and combined online/offline test for digital signal processing circuits. We complement these with cost-effective techniques for concurrent test of DSP circuits. Perhaps though where the most stringent challenges in the test arena are to be felt in the coming years is the area of Diagnosis, particularly when the ever more prevalent self-test techniques are utilized. We outline approaches in "Diagnosis for Scan-based BIST" in this talk that can be used to provide rapid resolution of failing scan cells from BIST signature information. These novel approaches can be used to ensure diagnosability from compact signature information and thus extend acceptance of self-test approaches to ever more niches of VLSI IC Test.