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Abstract
Aggressive microprocessor design methodologies using gigahertz clock
and very deep sub-micron technology are necessitating the use of
at-speed testing of small and distributed timing defects caused by
process variations during manufacturing. A primary objective of such
tests is to test for the faults that can lead to performance
degradation, such as delay faults. However, at-speed testing using
external tester is not an economically viable scheme and hardware BIST
leads to unacceptable performance loss and area overhead. A new
paradigm, instruction-based self-testing, can alleviate these problems
as it uses processor instructions to deliver the test patterns and
collect the test responses. Also, it has the ability to link to low
level fault models and it is well-suited methodology for testing
processors, embedded processor cores, IP cores, and SoCs. Moreover, the
same test can also be used for online periodic testing of processors to
improve the reliability.This
thesis proposes an instruction-based self-testing methodology for delay
fault testing of modern processors in a chronological way by first
dealing with non-pipelined processors, and then pipelined processors
and superscalar processor architectures.
In
order to test a non-pipelined processor a graph theoretic model, called
instruction execution graph based on the register transfer level
description of the processor is developed. This model, in conjunction
with the structural and functional information, is used to identify and
classify all paths into functionally testable and untestable paths and
to generate tests and test instruction sequences that can be applied in
functional mode of operation of the processor. The completeness of the
test method is guaranteed by extracting constraints for the paths that
are testable.
The approach proposed above
is expanded to include pipeline architectures. A new graph model,
called pipeline instruction execution graph, is defined that captures
the effect of executing multiple instructions concurrently. This graph
model is then used to generate tests and test sequences for normal as
well as forwarding paths between different stages of a pipeline
processor.
Finally, the thesis explores
path delay testing of superscalar architectures, one of the most
complex architectures of the modern processors. Such architectures use
out of order execution technique to enhance the throughput, which poses
serious challenges to instruction-based testing. This thesis identifies
test related issues. It proposes a superscalar processor model, called
superscalar instruction execution graph, and provides a method of
generating test programs that can force scheduler to execute the
instructions in the desired order to test the processor.
The
effectiveness of all the above stated approaches has been demonstrated
through experimental results for some representative processors.
’ȯ’ɽ’¹¼’³µ
G’¥¿’¥ó’¥Ñ’¥¯’¼Á’¶¦’Ìò’·¿’¼õ’ÍÆ’ÂÎ’¡ÊGPCRs’¡Ë’¤Ï’¡¢’»Ô’ÈÎ’Ìô’ʪ’¤Î4’³ä’°Ê’¾å’¤ò’À꒤ᒤ뒡¢’ÁÏ’Ìô’¤Ë’¤ª’¤±’¤ë’½Å’Í×’¤Ê’ɸ’Ū
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’Íø’ÍÑ’¤·’¤Æ’¡¢’ʬ’»Ò’ɽ’ÌÌ’¤Î’¤É’¤³’¤Ë’¥¤’¥ó’¥¿’¡¼’¥Õ’¥§’¡¼’¥¹’¤¬’°Ì’ÃÖ’¤¹’¤ë’¤«’¤ò’ͽ’¬’¤¹’¤ë’¼ê’Ë¡’¤ò’³«’ȯ’¤·’¤¿’¡£’¥í’¥É’¥×’¥·’¥ó’¡¢’£Ä2’¥É’¡¼’¥Ñ’¥ß’¥ó’¼õ’ÍÆ’ÂÎ’¡¢’¦Â2’¥¢’¥É’¥ì’¥Ê’¥ê’¥ó’¼õ’ÍÆ’ÂÎ’¤Ê’¤É’¡¢’¥¤
’¥ó’¥¿’¡¼’¥Õ’¥§’¡¼’¥¹’¤¬’´û’ÃÎ’¤Î’¥¯’¥é’¥¹AGPCRs’¤Ë’Ŭ’ÍÑ’¤·’¤¿’¤È’¤³’¤í’¡¢’ͽ’¬’ÎÎ’°è’¤Ï’¼Â’¸³’Ū’¤Ç’Äó’°Æ’¤µ’¤ì’¤Æ’¤¤’¤ë’ÎÎ’°è’¤È’°ì’Ã×’¤·’¤¿’¡£’½¾’¤Ã’¤Æ’¡¢’²æ’¡¹’¤¬’³«’ȯ’¤·’¤¿’¼ê’Ë¡’¤Ï’¥¯’¥é’¥¹A
GPCRs ’¤¬’¥ª’¥ê’¥´’¥Þ’¡¼’²½’¤¹’¤ë’ºÝ’¤Î’¥¤’¥ó’¥¿’¡¼’¥Õ’¥§’¡¼’¥¹’¤ò’¸¡’½Ð’¤¹’¤ë’¼ê’Ë¡’¤È’¤·’¤Æ’Í’ÍÑ’¤Ç’¤¢’¤ë’¤È’¹Í’¤¨’¤é’¤ì’¤ë’¡£’¤½’¤³’¤Ç’¡¢’¥¤’¥ó’¥¿’¡¼’¥Õ’¥§’¡¼’¥¹’¤¬’̤’ÃÎ’¤Î’¥¯’¥é’¥¹A
GPCRs’¤Ø’Ŭ’ÍÑ’¤·’¤¿’¡£
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Accumulating pharmacological and biochemical evidences have indicated
that some G-protein-coupled receptors (GPCRs) form homo oligomers,
hetero oligomers or both. The GPCRs oligomerizations are considered to
be important for proper signal transduction. Furthermore, in some
cases, the oligomerization has been suggested to be related to
diseases. Therefore, an accurate prediction of the residues that
interact upon oligomerization would further our understanding of signal
transduction and the diseases in which GPCRs are involved. One of the
complications for such a prediction is that the oligomerization
interfaces differ with the subtypes, even within the same GPCR
subfamily. Focusing on the distribution of residues conserved on the
molecular surface in a particular subtype, we developed a new method to
predict the interface for the GPCR oligomers, and applied it to several
subtypes of known GPCRs to check the sensitivity. Subsequently, we
found that predicted interfaces of rhodopsin, D2 dopamine receptor and
’¦Â2 adrenergic receptor agreed with the experimentally suggested
interfaces, despite difference in the interface region among the three
subtypes. Moreover, a highly conserved residue detected from the D2
dopamine receptor corresponded to a residue involved in a missense
change found in the large family of myoclonus dystonia. Our observation
suggestes the possibility that the disease is caused by the disorder of
the oligomerization, although the molecular mechanism of the disease
has not been revealed yet. The benefits and the pitfalls of the new
method will be discussed, based on the results of the applications.
Abstract
In the current network management, operators have to implement their
network to fit their management policy.
The management policy is a set of demands from customers
and mandates from business administrations
such as delay limits and usable bandwidth, capacity limit controls
and so on.
However, the management policy
is too abstract so that more specific description and processing are
required for generating configuration for each individual component as
their reflections.
The goal of my research is
to design and implement Policy Based Route Management (PBRM) methods:
namely to give measures for operators to describe their preferences on
route selections, to convert their descriptions to the actual router
configurations, and to confirm the network to fulfill the requirements
and keep its consistency.
According to the current routing management architecture, we have to
split our efforts into two categories: inter-domain and intra-domain
networks.
For the inter-domain network management, Routing Policy Specification
Language (RPSL) is standardized by Internet Engineering Task Force
(IETF) as a method to express an autonomous system's (AS's)
routing policies. The RPSL was widely
deployed, and operators can register their policies written in RPSL to
Internet Routing Registry (IRR) and generate router configurations with
a tool called IRRToolSet. However, if description on primary route,
which is vital route for their network operation, is missing, the
connectivity may be lost between routers when we apply the automatic
generated configurations to the routers. To establish the PBRM for
inter-domain networks, a mechanism to maintain the consistency of the
policy is highly required. In my research, the mechanism called Policy
Check Server is proposed. The Policy Check Server is a system to check
consistencies between AS's policies that are submitted by multiple
network operation entities. In the case an operator registers its
autonomous system's routing policies to the IRR, Policy Check Server
examines if the policies are consistent with the peer AS's policies.
This Policy Check Server is implemented and in operation at JPNIC as its
first step of deployment.
On the other hand, in the intra-domain network, there are few tools to
establish PBRM so far. In the management of the intra-domain network,
tools with Simple Network Management Protocol (SNMP) capability are
widely used. Although SNMP tools can set OSPF link costs to various
routers, operators still have to decide the actual values of the cost
manually. This is a nature to cause misconfiguration of routers and
instability of networks, so that an automation tool to ease operators'
burden is highly expected. However, there has been no study that tried
to establish a method that generates link costs from policies. In my
research, the system with both automatic generation of link costs and
consistency check with management policies is proposed.
In this dissertation, background and "needs" of the PBRM are revealed,
then the details of two system proposed in my research are discussed.
Through the deployment of my systems, the value and usefulness of my
systems are confirmed, however, several issues discussed in the later
section of this dissertation are also raised as the future work. In
general, PBRM is my first step toward the policy based network
management. There are multiple potential directions of this research.
Their discussions are also included to this dissertations.
’ȯ’ɽ’¹¼’³µ
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Abstract
Due to the chip density increasing drastically, power consumption
becomes one of the most important factors of VLSI design. Furthermore,
power and energy consumption of digital systems are considerably higher
in test mode than in normal mode. This extra power consumption leads to
many drawbacks, such as, decreased reliability, loss of yield,
increased product cost, difficulty in performance verification, reduced
autonomy of portable systems and so on. Hence, many techniques have
investigated power minimization or power constraints test.
This thesis proposes several schemes and approaches
to reduce peak power as well as average power at RT-level and at gate
level respectively. Test application time and hardware overhead are
also important factors. In our approaches, we try to minimize one or
either under the given power constraints to make the test more
effectively.
Focused on power reduction of RTL data path, this
thesis proposes three non-scan BIST schemes, formulates three problems
concerning the schemes, and introduces three power-constrained DFT
algorithms to resolve these problems.
In adjacent non-scan BIST scheme, some registers are
enhanced to test registers so that each functional module can be tested
by test registers connected with the module directly or only through
multiplexers. Though this scheme achieves short test application time,
hardware overhead is very high. To overcome this problem, in the
techniques of our laboratory, TPGs and RAs are placed only at PIs and
POs respectively, and test patterns and test responses are transferred
along paths in the data paths. We call this BIST scheme boundary
non-scan BIST scheme. We also propose a more general BIST scheme that
covers the above two schemes, adjacent non-scan BIST scheme and
boundary non-scan BIST scheme. Generally, TPGs and RAs can be placed
not only at the boundary of the data path but also inside of the data
path. Any register inside the data path can be a candidate to be
augmented to a TPG or an RA. We call this BIST scheme non-scan BIST
scheme.
We formulate three problems employing the above
testabilities satisfying peak power limit to minimize test application
time, hardware overhead and either respectively. Three
power-constrained DFT approaches are given to solve them. The first is
for adjacent non-scan BIST scheme intend for short test application
time. The second algorithm uses a boundary non-scan BIST scheme that
focuses on achieving a low hardware overhead. This scheme, therefore,
is more efficient in reducing the hardware overhead than previous
methods. The third algorithm is based upon a general non-scan BIST
scheme that explores possible trade-offs between hardware overhead and
test application time under power constraints, rather than consider
only one such factor, as previous published power-constrained methods
do.
Focused on power reduction of the circuits at gate
level, this thesis also proposes a low power scan test scheme and
formulates a problem based on this scheme. In this scheme the
flip-flops are grouped into N scan chains. At any time, only one scan
chain is active during scan test. Therefore, both average power and
peak power are reduced compared with conventional full scan test
methodology. To resolve this problem, a tabu search-based approach is
described to minimize test application time. In this approach we handle
the information during deterministic test efficiently. For various
benchmark circuits, this approach drastically reduces both average
power and peak power dissipation at a little longer test application
time.
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Abstract
The prediction of protein function using the sequence is
one of the important research topics in bioinformatics.
Meanwhile, the statistical characteristics of oligopeptide,
relatively short subsequence, have been investigated.
The main results of research include a new method based on oligopeptides.
The research demonstrates that `oligopeptide' enable us
to develop an effective method for predicting various protein function.
A known function of a protein is regarded to be inherited to its oligopeptides,
and the correspondence between oligopeptides
and the function is calculated in the whole proteins.
In the proposed method,
unknown functions of proteins are predicted
by means of the correspondence automatically.
Broad Applicability and High Performance:
The prediction performance of the method is measured for several functions
including GO terms and enzyme activities
by recall-precision graphs
using the 28,520 whole human proteins registered in RefSeq.
In most cases on GO terms, it scores 70% recall with 80% precision.
The proposed method is applicable in broad levels
from a specific enzyme to large class of enzymes like 'transferases' (EC 2.-.-.-).
In some cases on enzyme activities, it scores the maximum f-measure over 0.9.
The results of these evaluation suggest that
the proposed method is quite efficient for various protein functions.
Better than Other Methods:
To clarify the performance of the proposed method objectively,
the research includes
a comparative research with some already proposed prediction methods
based on homology search and pattern matching.
For instance, on the prediction of protein-tyrosine kinase,
The f-measures of homology search and pattern matching are 0.860 and 0.297, respectively,
while the proposed method based on oligopeptides scores maximum f-measure of 0.932.
The results of these evaluation suggest that
the proposed method based on oligopeptides
is more efficient than ones of homology search and pattern matching.
Consideration on Length of Oligopeptides:
The research also characterises
the relation between the length of oligopeptides
and the prediction of protein functions.
The performance of prediction is measured
for the length of oligopeptides between 1 and 9.
The results suggest that: 1) shorter oligopeptides than 4 are obviously less effective,
2) longer oligopeptides than 4 are almost equally effective, and
3) oligopeptides of 4 are intermediate.
The prediction based on oligopeptides utilises coexistence of oligopeptides among proteins.
The longer oligopeptides are more versatile than the shorter one
because the longer oligopeptide is more varied than the shorter one,
and the degree of the coexistence is inversely related to the length.
The results of these evaluation suggest that
length of 5 is quite effective and versatile.
The public hearing will be in Japanese.
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important how to achieve QoS which meets user's requirements within
these restrictions.
With the development of mobile systems and wireless networks, various
kinds of mobile terminals become part of distributed multimedia
systems. However, the restrictions, especially the limitation of battery
amount restricts the quality of video/audio playback, leading to the end
user's dissatisfaction.
So, we need a technique to adapt application-level QoS for end mobile
users depending on battery amount.
With the development of distributed multi-media systems, the performance
of end terminals and user's requirements become manifold. In order to
provision multimedia streaming services to multiple users, the
multi-media systems should be highly functional, scalable and
robust. For this purpose, the traditional server/client architecture is
already obsolete. Instead, we need a new architecture including an
efficient delivery network based on peer-to-peer overlay network and
functional components distributed among multiple distant
nodes for accommodating a large number of users and continuing
multimedia services even with node/link failures.
In order to guarantee the performance and/or appropriateness of QoS
adaptation mechanisms implemented as a software system, it is important
to test whether each mechanism is correctly implemented, without
executing the whole system.
So a new method for testing QoS in multimedia systems is indispensable.
This thesis provides the following three research topics.
First, in order to guarantee the correctness of QoS adaptation
mechanisms, we propose a testing method for QoS functions in distributed
multi-media systems.
In the proposed test method, we use a statistical approach where test
sequences take samplings of actual frame rates and/or time lags when an
IUT (implementation under test) is executed, and report test results
from ratio of samplings with low quality below a threshold in a normal
distribution of all samplings.
Secondly, a QoS adaptation method for streaming video playback for
portable computing devices where playback quality of each video segment
is automatically adjusted from the remaining battery amount, desirable
playback duration and the user's preference to each segment, is
proposed. In this method, we assume that video segments
are classified into several predefined categories. Each user specifies
relative importance among categories and preferred video property such
as motion speed and vividness for each category. From the information,
playback quality and property of each category are determined so that
the video playback can last for the specified duration within the
battery amount.
Finally, a new video delivery method called MTcast (Multiple
Transcode based video multicast) is proposed. It achieves efficient
simultaneous video delivery to multiple users with different quality
requirements by relying on user nodes to transcode and forward video to
other user nodes. In MTcast, each user specifies a quality requirement
for a video consisting of bitrate, picture size and frame rate based on
the user's environmental resource limitation. All users can receive
video with the specified quality (or near this quality) along a single
delivery tree.
Some experimental results show that our proposed test method works
effectively for QoS functional tests in a typical multimedia playback
program, and our QoS adaptation method improves playback quality of
important categories a few times better than flattening the playback
quality. Through simulations, our video delivery method can achieve
much higher user satisfaction degree and robustness against node failure
than the layered multicast method.
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Abstract
This research proposes an architecture to interconnect different traceback
systems for tracing attacks beyond the operational barriers
on the inter-domain network and for tracking attacks narrow down
from layer 3 traceback to layer 2 traceback on the intra-domain network.
In order to defend attacks on the Internet, traceback techniques are
requiredas well as attack detection techniques and attack protection techniques.
Network operators can manually trace back attacks, but it is likely to be
tedious process and spends much more time.
Many researcher have proposed various traceback techniques to automate
the manual traceback, however, they faced several difficulties.
On the inter-domain traceback, the issues arise from the difficulties to
overcome the barriers on network operation boundaries, especially the leakage of
sensitive information, the violation of the administrative permission,
the difference of employed techniques among Autonomous Systems (ASes) and
the cooperation among ASes.
On the other hand, the challenge of the intra-domain traceback is how to
detect the attacker node inside a network domain even when both the source
IP address and the source MAC address of an attack packet are spoofed.
The interconnection between layer 3 traceback techniques and layer 2 traceback
techniques is also an issue of the inter-domain traceback because most
traceback techniques on each layer cannot track attacks on other layer.
In this research, we propose InterTrack as an interconnection architecture
for traceback systems, Ingress Port Based Tracking (IPBT) method as
a layer 2 tracback technique, and L2-SPIE as a technique to interconnect
a layer 3 traceback and a layer 2 traceback.
The contributions of this research are
as follows:
The loose cooperation among ASes on the deployment traceback systems and
on traceback operation:
We designed the InterTrack architecture and InterTrack messages for the loose cooperation among ASes.
The ITM trace reply message contains only the reverse AS path information,
and it doesn’¡Çt contain the detailed topologies of ASes.
Through the module components, ASes can choose traceback techniques
for the internal use in accordance with the pros and cons of each technique
or the investment cost.
The same manner of the traceback operation as the manner of other network operations:
The phased tracking approach of InterTrack was designed along with
the network operation boundaries on the routing operation.
By phasing an inter-domain traceback into four stages,
ASes can authorize the users on each stage.
ASes can also delegate the internal traceback operation to
the organizations on the IGP sub-domains.
Expedition of the procedures on the inter-domain traceback:
The preliminary experiments of InterTrack show that the average time of
a trial on InterTrack was estimated as 14 seconds with a hash digest logging
based border tracking system in 9 AS hop length.
The model of the border tracking technique for identifying upstream neighbor
ASes:
We modeled the border tracking technique for detect the neighbor ASes on the attack path.
According to this model, we developed a sample border tracking implementation
by using PAFFI, a hash digest logging based traceback product.
The detailed internal inspection about the source of an attack packet:
Our IPBT method can track back a single packet on a layer 2 network to
the port to which an attacker node connects despite the source spoofed
characteristic of the IP address and the MAC address.
An interconnection between a hash digest logging method on the layer 3 traceback and IPBT method on the layer 2 traceback:
We developed a prototype implementation of L2-SPIE which interconnects
hash digest loggin method as a layer 3 traceback and our IPBT method as
a layer 2 traceback.
The evaluation result shows the average time of a traceback trial on L2-SPIE was about 1,500 microseconds.
The foundation of the self-defending network architecture:
InterTrack and L2-SPIE provide a multi-layers traceback to detect
the attacker nodes from the layer 3 traceback to the layer 2 traceback.
We also designed InterTrack to cooperate other detection systems and
protection systems for the multi-layers traceback
and the attack mitigations.
In the presentation, I talk about the details of these proposals.
The public hearing will be in Japanese.
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