October 18-24, 2009, Changsha, China
The 8th International Conference on ASIC (ASICON2009)
Computer Design and Test Laboratory : D2

Paper summary

The paper presented in the conference is entitled, “F-Scan: An Approach to Functional RTL Scan for Assignment Decision Diagrams”. It proposes a new methodology for functional Register Transfer Level (RTL) scan, in which existing functional elements and paths can be maximally utilized. The approach is called F-scan, which primarily aims to reduce the total area overhead due to augmentation for testing. Since the method allows parallel scanning of test vectors, test application time is also made to be at the minimum. The case study shows the effectiveness of our approach compared to full scan design. In the presentation, preliminary experimental results on small benchmark circuits are also shown.
This paper has been recognized among the 160 other oral papers accepted and is rewarded with the Excellent Student Paper Award.

Overview of the conference
ASICON 2009 is the 8th of this conference series, which is held once every two years. It took place at Preess Resort & Hotel in Changsha, China from October 20 to 23, 2009. The conference provides an international forum for VLSI circuit designers, ASIC users, system integrators, IC manufacturers, and CAD/CAE tool developers to present latest results and developments in their respective fields. It is also a platform for exchange of academic and technical information among attendees. The venue was indeed conducive for learning.
In this ASICON, 552 papers were received from 16 countries and areas. After an intensive paper review process by more than 90 experts, 160 oral papers and 41 invited papers have been accepted by the technical program committee of ASICON 2009. That is 36.4% acceptance rate. Poster papers were also accepted with the rate of 24.1%. Aside from the technical sessions, keynote speeches were also given during the plenary sessions. An interesting speech was given by Frank Chang from University of California, Los Angeles, which was about Terahertz CMOS Circuit Design and Applications for Future Communication/Imaging Systems. He introduced the capability of using terahertz waves for imaging, which is better than infrared or sonar, especially in capturing images during foggy conditions. Applications range from vehicle enhancements to network-on-chip communication. Still at an early stage, further developments will lead to a future of using terahertz waves. As of now, the means of producing these high frequency waves effectively and efficiently is still being researched on.
The technical sessions are divided into five different conference rooms, arranged according to the topics of the papers to be presented. This conference catered to a wide range of fields in VLSI design and testing, which includes several applications on communication and multimedia. My session is 5B: Testing and Reliability (1). After the first two invited papers, I introduced my paper. The first invited paper is truly remarkable for it aims to solve a great concern in the field of testing today. DART, which is a circuit failure prediction mechanism, is a system for online failure prediction and degradation/fault detection, which is necessary in order to minimize (or prevent) problems caused by sudden malfunction of circuits during operation or simply, due to aging. In this report, the topic that caught my attention is the thermal control for accurate delay testing. Here, a means of testing the circuit such that temperature variation is very minimal is targeted. A way to deal with changing seasons and weather (environmental temperature) is also a concern. I would like to be able to do some research on this topic in the near future.

Opinion exchange

I am very glad to have received a lot of interest from the session 5B attendees regarding my paper. Several questions have been asked and discussions continued during the coffee break. Questions range from my current results (number of test vectors: is it different from full scan?) to more detailed explanation of the F-Scan method and the generation of test environment. Given 12 minutes of presentation time and 3 minutes of question and answer, I was able to respond to as much questions as possible. During the break, my professor, Prof. Fujiwara, and I conversed with Prof. Cheng-Wen Wu, a famous professor of the Industrial Technology Research Institute of Taiwan, and explained further that any model can be considered for F-Scan because it has the same testability as gate-level full scan, in response to his earlier question. I also sat down with a student from Tsinghua University and discussed my work.
Other things discussed ranged from different topics such as: the use of RTL circuit benchmarks and circuit testing during summer (its effect on temperature variation), among others. With these exchanges, I have expanded my knowledge and understanding of my field and the other researches done by others. I hope I was also able to encourage others with my work.

Other activities during the trip

Before the conference, I was able to visit Prof. Zhiqiang You and his laboratory in Hunan University.  I was also able to attend the talks given by professors from our laboratory to Software School students of Hunan University.