Computing Architecture

Research Staff

  • Prof.Yasuhiko Nakashima

    Prof.
    Yasuhiko Nakashima

  • Prof. Mutsumi Kimura

    Affiliate Prof.
    Mutsumi Kimura

  • Assoc.Prof.Takashi Nakada

    Assoc.Prof.
    Tkashi Nakada

  • Assist.Prof. Tran Thi Hong

    Assist.Prof.
    Tran Thi Hong

  • Assist.Prof. ZHANG, Renyuan

    Assist.Prof.
    Renyuan Zhang

E-mail { nakashim, nakada, hong, rzhang }[at] is.naist.jp

Research Area

Power Efficient Near-Data Memory Array Accelerators for Post-Moore Generation

Research and development on highly efficient computing systems, accelerators and LSIs for image processing and big data processing, such as graph processing and machine learning

EMAX2: Memory-centric accelerator LSI for graph processing and stencil computation

EMAX4: High performance accelerator platform with heterogeneous commercial LSIs

EMAXV,VR: Large-scale CGRA for image recognition

IMAX: Small footprint near-memory accelerator for AI

Compact and Efficient Approximate Computing VLSIs for Post-Moore Generation

Research and development on reconfigurable approximate computing VLSI architectures with compact circuits, low energy, and function-flexibility for multi-operand computations, which can be efficiently employed in parallel computing tasks.

Acceleration of deep learning applications such as CNN by using analog computational cores

ACU: general purpose reconfigurable Approximate Computing Units for parallel computations

Various non-binary-based computing methodologies such as neuromorphic and stochastic computing for Post-Moore generation

Exploring analog-digital-hybrid CGRA platform

Neuromorphic LSIs for Post-Moore Generation

Research and development on neuromorphic integrated systems for artificial intelligence of super compact and low power.

Amorphous metal-oxide semiconductor thin-film synapses for 3D structure

Neuromorphic architecture and leaning rule for astronomical scale integration

Brain-type integrated system with artificial humanity

Energy efficient system architecture for next generation machine learning

Research and development on next generation machine learning system architecture with edge computing.

Design methodology for next generation machine learning systems

Spatiotemporal computation/data/communication optimization among edge and cloud computing

Aggregation and compression for intermediate data in deep learning system

Probabilistic reasoning algorithms with Bayesian networks

IoT + Blockchain for secure smart systems

IoT and blockchain technologies are combined to develop smart systems such as smart healthcare system, smart city management, etc. Secure health monitoring system for hospital is currently under researched.

Wireless Communication for IoT

Research and develop a low-cost low-power wireless communication transceiver for IoT applications. The transceiver follows IEEE 802.11ah standard. In this research we focus on two layers: Physical (PHY) and Medium Access Control (MAC). The research basically has two stages: (1) software simulation on software (using Matlab, C) to check the Bit Error Rate (BER) performance, throughput (data rate), etc. of system; (2) hardware circuit design (using Verilog, Simulink, Modelsim, FPGA, etc.)

VIT_DEC: A low complex K-best Viterbi decoder for error correction

FEC_CONCAT: concatenating several FEC types such as LDPC, BCC, etc.

Energy simulation of IoT sensor networks

BER/PER simulation and hardware prototypes of the 802.11ah PHY layer

802.11ah MAC protocol

Key Features

In our laboratory, we study state-of-the-art technologies for next-generation computing paradigms. Our goal is to realize environment-friendly, high-performance, and robust computer systems under energy constraints. From a wide viewpoint (from new theories to LSI implementations), we promote cutting-edge research and the highest degree of education within various research themes, particularly: high-performance, low-energy and dependable computation, and hardware/software co-design.

Research collaboration

Socio Next, Konica Minolta

Fig.1: Power Efficient Near-Data Memory Array Accelerators and FPGA Systems

Fig.1: Power Efficient Near-Data Memory Array Accelerators and FPGA Systems

Fig.2:Analog Acelerators

Fig.2: Analog Acelerators

Fig.3:Analog Neural Network LSIs

Fig.3: Analog Neural Network LSIs

Fig.4:Blockchain for IoT

Fig.4: Blockchain for IoT

Fig.5: Wireless Communication for IoT

Fig.5: Wireless Communication for IoT