Computing Architecture

Research Staff

  • Prof.Yasuhiko Nakashima

    Prof.
    Yasuhiko Nakashima

  • Assoc.Prof.Takashi Nakada

    Assoc.Prof.
    Tkashi Nakada

  • Assist.Prof. Tran Thi Hong

    Assist.Prof.
    Tran Thi Hong

  • Assist.Prof. ZHANG, Renyuan

    Assist.Prof.
    Renyuan Zhang

E-mail { nakashim, nakada, hong }[at] is.naist.jp

Research Area

High performance, low-power and near-data-intensive memory array accelerators

Research and development of highly efficient computing systems, accelerators and LSIs for image processing and big data processing, such as graph processing and machine learning

Acceleration of graph processing and stencil computation on modern 120-core environments and commercial accelerators (GPU and Xeon Phi)

Large-scale FPGA-based accelerators for image and graph processing

LAPP: A high performance accelerator LSI with processing element arrays using standard scalar instruction sequences

EReLA: A dependable and high performance accelerator LSI with redundant execution functionality on processing elements arrays

EMAX2: A memory-centric accelerator LSI for graph processing and stencil computation

EMAX4: A high performance accelerator platform with heterogeneous commercial LSIs

EMAX5: A large-scale CGRA for image recognition

PyCoRAM: A productive programming model with high-level synthesis and hardware resource abstraction for FPGA-based accelerators

Pyverilog: A toolkit for static analysis of hardware description, and its applications

Ultra small dependable processors for printable sensors

Research on small and ultra dependable processor architecture for next generation LSIs using new materials

OROCHI: A heterogeneous multi-ISA processor with hardware-centric dynamic instruction translation

DEP: Dependable processing element architecture through self-sustaining circuit recovery

RM: An emulation-based small computing system for legacy software

EMIN: Efficient emulation technology on 8-bit small computers for modern 32-bit software

REMIN: A dependable CPU with dynamic instruction translation to avoid circuit failures

FCOMP: An 8-bit ink-jet film computer executing 32-bit operating systems with emulation technology

NCHIP: An analog neural network for image recognition

Extremely defect free computers

Research and development of highly dependable computers with resistance to cosmic radiation. We use a real alpha-ray source for our LSI evaluations

DARA: A dependable CPU achieved through cooperation of multiple independent pipelines

BDMR: Reliable processor architecture

Asymmetric processor architecture for irregular applications

Research on complicated processor architecture for irregular applications containing many pointer chain accesses and recursive calls

CAMP: A crazy CPU created by reusing past computation results and speculative parallel executions using CAM (Content Addressable Memory)

IoT system architecture

Research on next generation IoT system architecture with trillion sensor nodes

Design methodology for next generation IoT systems

Spatiotemporal task/data/communication optimization

Edge computing on advanced sensor nodes

Adaptive task scheduling for near real time applications

Dependable sensor networks for trillion sensor nodes

Next generation WiFi for IoT

Research and develop a low-cost low-power wireless communication transceiver for IoT applications. The transceiver follows IEEE 802.11ah standards. In this research we focus on two layers: Physical (PHY) and Medium Access Control (MAC). The research basically has two stages: (1) software simulation on software (using Matlab, C) to check the Bit Error Rate (BER) performance, throughput (data rate), etc. of system; (2) hardware circuit design (using Verilog, Simulink, Modelsim, FPGA, etc.)

VIT_DEC: A low complex K-best Viterbi decoder for error correction

FEC_CONCAT: concatenating several FEC types such as LDPC, BCC, etc.

Energy simulation of IoT sensor networks

BER/PER simulation and hardware prototypes of the 802.11ah PHY layer

802.11ah MAC protocol

Key Features

In our laboratory, we study state-of-the-art technologies for next-generation computing paradigms. Our goal is to realize environment-friendly, high-performance, and robust computer systems under energy constraints. From a wide viewpoint (from new theories to LSI implementations), we promote cutting-edge research and the highest degree of education within various research themes, particularly: high-performance, low-energy and dependable computation, and hardware/software co-design.

Research collaboration

Socio Next, Konica Minolta, Huawei

Fig.1:Processor architecture with high performance and low energy

Fig.1: High Performance, Low-Power and Near-Data-Intensive Memory Array Accelerator

Fig.2:Printable, flexible film computer

Fig.2: Accelerators for Light-field Image Processing and Image Recognition

Fig.3:Energy Efficient Scheduling for Smart Sensor Nodes

Fig.3: Energy Efficient Scheduling for Smart Sensor Nodes

Fig.4:FPGA  Design Frameworke

Fig.4: FPGA Design Framework