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Dependable System

Today's information society is supported by various level of advanced technology such as applications, systems, computers and VLSIs. The Dependable System Laboratory is pursuing research on safe and secure systems including distributed systems with hundreds of computers and VLSIs with billions of transistors. "Dependability" is the concept from user's point of view that we can use systems reliably and securely.
In order to realize dependable systems, we need to consider various aspects of the systems from user's point of view. For example, all the systems are completely tested and the bad systems should not be shipped, the systems can work correctly in the presence of faults, the systems can predict and avoid system failure caused by transistor aging, and the system can handle the malicious users. This laboratory is pursuing research to improve dependability from various approaches.

〈教　員〉 Prof. Michiko INOUE
Prof. Kazumi HATAYAMA
Assist. Prof. Tomokazu YONEDA and Yuta YAMATO		 Laboratory's HP
Prof. INOUE
Prof. INOUE

Research Areas

VLSI Design and Test

Overcome the VLSI design and test challenges derived from scale enlargement, process miniaturization, high performance and low power.

  • VLSI Design for Testability
  • Design and Test for 3D-LSIs
  • High Quality Test (Timing-Related Faults, Low-Power Test, Low-Temperature Test etc)
  • Fault Detection and Diagnosis of VLSIs
  • Software-Based Self-Test for High Performance Micro-Processors
VLSI design and test flow
VLSI design and test flow

Reliable and Dependable System
  • Test Architecture for Failure Prediction
  • Circuit and System Mechanisms for High Field Reliability
DART: Dependable Architecture with Reliability Testing
DART: Dependable Architecture with Reliability Testing

Distributed Algorithms
  • Fault-Tolerant Distributed Systems
  • Wait-Free Distributed Algorithms
Parallel Algorithms
  • Parallel Algorithms for Multi-Core Processors
  • Parallel Algorithms for LSI CAD

Facilities

Comfortable research environments are supported with high performance servers, workstations, high resolution displays, latest EDA（Electronic Design Automation） tools, test tools. Newly introduced SSD equipped servers make the environment more comfortable.

Hardware
SunBlade X6270, Sun SPARC Enerprise 5000 　SunFire X4270 M2 with 640GB SSD, 　SunStorage F5100, Apple iMac 27-inch
Software
Intel Parallel Studio XE (Win, LINUX)
Synopsys University Program(CAD tools):
・DesignCompiler, PrimeTime, VCS, HSPICE etc.
DFT (Design-for-Test) tools:
・TurboDFT,TurboBSD, TurboBIST-Logic(SynTest),
　 SIGNOFF, HiDFT-STAR(DeFacTo)
ATPG (Test Generation) tools:
・Encounter Test (Cadence), TetraMAX ATPG(Synopsys)
Thermal Analyzer:
・FloTHERM(MentorGraphics)

Feature of the Laboratory

The members of the Dependable System Lab are tackling several problems on dependability. Through the research, students get the skills of theoretical thinking, presentation, design and analysis of algorithms, traditional C/C++ and Java programming, advanced multi-thread programming, and Verilog/VHDL hardware programming through the research.

Joint Projects

JST CREST
  • Test Methods for High Field Reliability of SoC/NoC
Joint Work with Industry
  • Research on Evaluation and Validation of Effectiveness of High Field Reliability Techniques for Reliability-Oriented LSIs (Hitachi Ltd.)

Resent Dissertaion and Theses

Master's Theses
Ratna Aisuwarya: Acceleration of Seed Ordering and Selection for High Quality Delay Test, September 2012. Thesis PDF
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